library verilog;
use verilog.vl_types.all;
entity vga_test is
    port(
        sys_clk         : in     vl_logic;
        sys_rst_n       : in     vl_logic;
        hsync           : out    vl_logic;
        vsync           : out    vl_logic;
        v_video_en      : out    vl_logic;
        h_video_en      : out    vl_logic;
        rgb             : out    vl_logic_vector(2 downto 0)
    );
end vga_test;
